A digital system may transmit data to another location via a high-speed serial link. The data may be split across multiple serial links to increase the data capacity of the connection, where the original data is reassembled from the multiple serial links at the receiving end. For example, transmit data (TX Data) generated at 64 bits per clock cycle may be split into two 32-bit words, each transmitted through its own serial link. A serializer, such as a parallel-in, serial-out (PISO) circuit, converts each 32-bit word into a serial stream of bits. At the receiver, a deserializer, such as a serial-in, parallel-out (SIPO) circuit, regenerates the 32-bit words. Because some loss of data alignment and skew between the serial links are common, specialized alignment logic may be required to properly reassemble the original 64-bit received data (RX Data).
According to some data transmission protocols, the width of the data clocked into the transmitter (e.g. 66 bits) does not match the width of data clocked into the PISO (e.g. 64 bits). A FIFO, commonly known as a “Gearbox FIFO,” is used to convert the data width from 66 bits to 64 bits. Because the system clock controlling the Gearbox FIFO and the transmitter clock controlling the PISO circuit of the transmitter may be at different frequencies, the system clock cannot be used as a reference for the phase adjustments of the transmitter clock.
Accordingly, circuits and methods that enable the transmission of data using a Gearbox FIFO and addressing transmitter inter-lane deskew are beneficial.